Many computers have multiple entities which require access to a single system memory. For example, multiple processors often compete for access to a single memory for reading and writing of data. Still other entities, such as timers, make periodic access requests to refresh memory. Because memory can not be accessed by more than one entity at a time, some mechanism must be provided to regulate and control multiple, simultaneous access requests.
Many computers have a memory controller to provide such regulation. One of the controller's duties is to arbitrate among competing requests for memory access. In the past, the priority order for granting multiple requests has been predetermined by the system design. This reduces the flexibility of the system and can decay its performance.